Tuesday, May 25, 2004

Tom's Hardware on NICs

Tom's Hardware wrote a good article titled Gigabit Ethernet: On-Board Chips Reviewed. It explains the importance of high bandwidth PCI buses. I recommend reading it, but keep in mind the following feedback I sent the site:


Hello,

I found your article "Gigabit Ethernet: On-Board Chips Reviewed" useful. I'm really glad to see someone authoritatively discuss NIC issues.

However, I think you use some throughput terms in odd ways. I believe a few changes could make it easier for the reader to appreciate your analysis.

For example, here you say "133 MB/s," presumably to mean 133 MegaBytes per second, for the bandwidth of a 32 bit 33 MHz PCI bus. That is correct. Farther down the same page, you mention "a 100 MBit interface," which I guess you mean 100 Megabits per second. Would it not be better to standardize on 133 MBps and 100 Mbps, respectively?

Just after that you say "2 GBit/s or 266 MBit/s". This is where you are mixing these terms and creating confusion. From the context the first term should be 2 Gigabits per second (2 Gbps) and the second should be 2 MegaBytes per second (266 MBps). I checked the Intel CSA document to confirm these values.

On the next page you write "The 100 MBit/s, 100BaseT-Ethernet standard offers a theoretical maximum data transfer rate of 12.5 MBytes/s (MB/s). In real world applications, the actual rate is usually 8 MB/s." I recommend this be changed to "The 100 Mbps, 100BaseT-Ethernet standard offers a theoretical maximum data transfer rate of 12.5 MBps. In real world applications, the actual rate is usually 8 MBps." I think other mentions of "MB/s" should similarly be replaced by "MBps" for clarity.

Thank you for your time,

Richard Bejtlich

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